研發工程師主管

1. High speed SerDes PHY design;
2. MIPI C/D PHY Serdes analog circuit design.

負責 Display Port IP 規劃與設計
工作內容:
 Display port IP leader
 Display port IP architecture definition
 RTL design and functional verification
 FPGA verification
 Synthesis and static timing analysis

Senior Analog circuit design engineer who meets one of following qualifications:
1. Proven track record on design of analog building blocks,
such as Bandgap reference, Charge pump, Regulator, Voltage reference.
2. Proven track record on design of high speed PHY and mixed-signal circuit,
such as High speed Transmitters and Receivers, DLL & DCC, PLL.
Familiar with DDR5 or LPDDR5 PHY design is a plus.
3. Proven track record on design of memory core circuit,
Such as Sense Amplifier, Word/Column Line driver and decoder, array architecture and floor planning.
Experience with DRAM design is a plus.

Verification of digital design ,most on serdes phy ip using UVM , including   
.standard spec study/design feature study
.simple vip creation or third parity vip survey
.vplan define
.building sb/assertion check ,stimulus by constraint random
.create covergroup /assertion cover for  functional coverage
.code coverage
.co –simulation with analog phy

1. Design RTL/Logic using Verilog
2. Simulate and develop IPs and Subsystems
3. Validate silicon and debug

1. 規劃集團 ESG策略
2. 制定集團大型專案計畫及相關執行方案
3. ESG團隊及業務管理

1.負責捷運專案的整體規劃、設計與實施管理。
2.確保項目在預算和時程內完成，並符合所有技術標準和規範。
3.協調內外部資源，管理項目的進度、風險與品質。
4.與政府機構、承包商、工程團隊保持有效溝通，解決專案中的各種問題與挑戰。
5.編制項目報告並向高層管理層匯報專案狀況，提出風險應對策略。
6.負責建立並管理項目團隊，確保各項工作順利進行。

*核心統籌： 負責大型廠辦或高標準IDC機房建置案管理。
*時程與策略規劃： 具備獨立作業能力，主導工程進度規畫、風險預判與關鍵路徑控管。
*現場協作與技術整合： 專案施工期間進駐工地，監督並管理分包商施工品質，負責複雜界面（Interfacing）的技術澄清、協調與跨團隊整合。
*品質與現場控管： 嚴格落實工地人員管理、工程日誌紀錄，並針對施工品質與安全標準進行深度稽核。
*利害關係人管理： 代表公司與業主（Client）及顧問單位進行專業對接，定期主持進度報告會議，解決專案歧見。