負責 Display Port IP 規劃與設計 工作內容: Display port IP leader Display port IP architecture definition RTL design and functional verification FPGA verification Synthesis and static timing analysis
Verification of digital design ,most on serdes phy ip using UVM , including .standard spec study/design feature study .simple vip creation or third parity vip survey .vplan define .building sb/assertion check ,stimulus by constraint random .create covergroup /assertion cover for functional coverage .code coverage .co –simulation with analog phy