IC design工程師(台北或新竹)

1. 主導合成製程技術的開發、精進製程良率與生產穩定度。
2. 負責合成專業人才之技術培訓，建立具專業標準的作業體系。
3. 成本控制、原物料耗損管理及研發/生產資源配置。
4. 品質體系驅動與改善。
5. 熟 DCS系統，落實高度自動化生產監控與安全管理。
6. 擴廠與建廠戰略規劃

Senior Analog circuit design engineer who meets one of following qualifications:
1. Proven track record on design of analog building blocks,
such as Bandgap reference, Charge pump, Regulator, Voltage reference.
2. Proven track record on design of high speed PHY and mixed-signal circuit,
such as High speed Transmitters and Receivers, DLL & DCC, PLL.
Familiar with DDR5 or LPDDR5 PHY design is a plus.
3. Proven track record on design of memory core circuit,
Such as Sense Amplifier, Word/Column Line driver and decoder, array architecture and floor planning.
Experience with DRAM design is a plus.

國際法規遵循、中英文合約審閱、國內外爭訟管理、法律風險管理、法律議題研究與諮詢，其他交辦事項。

國際法規遵循、中英文合約審閱、國內外爭訟管理、法律風險管理、法律議題研究與諮詢，其他交辦事項。

PMIC
DC to DC
產品:車用/電池/PC/CHARGER

1. High speed SerDes PHY design;
2. MIPI C/D PHY Serdes analog circuit design.

Verification of digital design ,most on serdes phy ip using UVM , including   
.standard spec study/design feature study
.simple vip creation or third parity vip survey
.vplan define
.building sb/assertion check ,stimulus by constraint random
.create covergroup /assertion cover for  functional coverage
.code coverage
.co –simulation with analog phy

1. Design RTL/Logic using Verilog
2. Simulate and develop IPs and Subsystems
3. Validate silicon and debug