General Company | Mid-level
專案主管
機構工程師｜ 網際網路相關業 ｜新竹市 ｜NTD 1,500,000~2,000,000 Actual salary is negotiated after interviews with hiring companies.
日期：2026/05/19 編號：F000013967
⭐️ Job Advantage
集團公司
Qualifications
網通系統產品機構設計經驗
Responsibilities
1.機構主管經驗
Ideal Candidate
1.專案機構主管經驗
Other Requirements
Education:Undergraduate
Department:No Limitations
Experience:Over 5 years of experience
Language:
English：Listening/Intermediate Speaking/Intermediate Reading/Intermediate Writing/Intermediate
Management Responsibilities:To be determined
Business trip:Need business trip for fewer than 1 months
Language:
English：Listening/Intermediate Speaking/Intermediate Reading/Intermediate Writing/Intermediate
Employee Benefits
Required by law:
勞保
健保
陪產假
產假
特別休假
育嬰留停
女性生理假
勞退提撥金
產檢假
就業保險
職災保險
其他值得一試的好工作
Listed | Specialty Personnel
FPGA 工程師
數位IC設計工程師｜自動控制相關業｜台北市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
VHDL
Verilog
RTL Coding
FPGA
上巿櫃IC設計褔利佳
1. FPGA implementation.
2. Integration of related FPGA (high-speed) interfaces.
3. System integration and verification.
4. FPGA Design, C/C++.
5. System simulation.
2. Integration of related FPGA (high-speed) interfaces.
3. System integration and verification.
4. FPGA Design, C/C++.
5. System simulation.
Listed | Specialty Personnel
研發工程師
數位IC設計工程師｜IC設計相關業｜新竹市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
RTL Coding
工作穩定 公司發展好
影像演算法、數位RTL Coding
General Company | Junior
電控主管
其他工程研發主管｜精密儀器相關製造業｜新竹縣市全區 ｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
PLC程式設計
1. Circuit diagram design 2. Equipment experiment data analysis and statistics 3. CE, SEMI certification design data collection 4. PLC, HMI programming, control logic planning and design 5. Equipment operation test 6. R&D plan execution 7. Other matters assigned by the supervisor
General Company | Specialty Personnel
工程師
數位IC設計工程師｜IC設計相關業｜新竹縣市全區 ｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
數位電路驗證
數位晶片產品開發
RTL
1.EDA TOOL 客戶端支持服務
2.客戶bug解決
2.必要時支援on-site support
3.需熟悉Verilog及IC Flow
4.具獨立處理問題能力。
2.客戶bug解決
2.必要時支援on-site support
3.需熟悉Verilog及IC Flow
4.具獨立處理問題能力。
General Company | Specialty Personnel
研發工程師主管
其他工程研發主管｜光學器材製造業｜新竹市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
機構設計
軟韌體開發
1. AOI programming, system design and integration
2. Software writing (C, C++, Visual C++, MFC)
3. Requires knowledge related to imaging (image processing, image sensor, image quality, tuning, calibration, camera modules)
4. Software interface program modification.
5. Machine vision software design
2. Software writing (C, C++, Visual C++, MFC)
3. Requires knowledge related to imaging (image processing, image sensor, image quality, tuning, calibration, camera modules)
4. Software interface program modification.
5. Machine vision software design
General Company | Junior
研發主管
其他工程研發主管｜印刷電路板製造業(PCB)｜桃園市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
新技術開發
1. 新製程設立
2. 新產品導入
3. 重要VE與製程優化
4. Trouble shooting
5. 技術趨勢掌握與交流
6. 客訴處理
2. 新產品導入
3. 重要VE與製程優化
4. Trouble shooting
5. 技術趨勢掌握與交流
6. 客訴處理
General Company | Specialty Personnel
研發工程師/主管
數位IC設計工程師｜IC設計相關業｜苗栗縣市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
RTL
1. TOP/Block physical implementation (28nm以下), 有12nm/7nm 經驗尤佳
2. IR rail analysis(Voltus/Redhawk)
3. Layout verification (Calibre DRC/LVS)
4. Timing closure (Tempus/PrimeTime/Tweaker)
5. Tcl/Perl/Makefile programming (有此技能者優先考量)
2. IR rail analysis(Voltus/Redhawk)
3. Layout verification (Calibre DRC/LVS)
4. Timing closure (Tempus/PrimeTime/Tweaker)
5. Tcl/Perl/Makefile programming (有此技能者優先考量)
Foreign Company | Specialty Personnel
Design Verification Engineer
數位IC設計工程師｜半導體製造業｜新竹縣市全區 ｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
數位ic設計
Product : OLED DDI
1. Develop integrated verification environment.
2. Verify designs with system verilog and system verilog assertion.
3. Develop and optimize verification flow and methodology.
4. Good knowledge of IC design flow.
5. Scripting experience using scripting languages like Perl and Python.
1. Develop integrated verification environment.
2. Verify designs with system verilog and system verilog assertion.
3. Develop and optimize verification flow and methodology.
4. Good knowledge of IC design flow.
5. Scripting experience using scripting languages like Perl and Python.
不符合你的期望嗎？
你可以先成為儲備人選，未來若有適合您的職務，我們將會主動與您聯絡。