主な能力
職務責任
2.full chip level simulation & verification
3.working with layout and CAD team
理想的な求人
以下符合幾項即可:
1.MS or above with major in EE related
2.familiar with EDA tools, such as virtuso
3.familiar with circuit simulation tools (HSPICE, finesim,etc.)
4.good knowledge of transistor level CMOS circuit design
5.experience in transistor level simulation
6.experience in memory circuit design is a plus
7.hand-on experience in verilog is a plus
その他条件
学科:物理科目,材料エンジニアリング,電機科目
経歴:職務経験3年以上
出張・出向:出張なし
会社の福利厚生