General Company | Specialty Personnel
IC design工程師(台北或新竹)
類比IC設計工程師/數位IC設計工程師｜ 半導體製造業 ｜新莊區‧五股區‧泰山區 ｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
日期：2026/04/24 編號：FC02015131
Qualifications
類比IC電路設計
Responsibilities
1. build up verilog testbench
2. fullchip verilog simulation/verification
3. verilog behavior models creation
4. pattern pool coverage raising up
2. fullchip verilog simulation/verification
3. verilog behavior models creation
4. pattern pool coverage raising up
Ideal Candidate
1. Digital IC design: Verilog, RTL, FPGA, Cell base ic design, Custom ic design
Experience in Design For Testing (DFT) and Built In Self Test (BIST)
2.3~5 years of practical experience in semiconductor product design and development
Experience in Design For Testing (DFT) and Built In Self Test (BIST)
2.3~5 years of practical experience in semiconductor product design and development
Other Requirements
Education:Master
Department:Physics,Materials Science & Engineering,Electrical engineering
Experience:Over 3 years of experience
Language:
English：Listening/Intermediate Speaking/Intermediate Reading/Intermediate Writing/Intermediate
Management Responsibilities:Not need to bear any management responsibilities
Business trip:No business trip required
Language:
English：Listening/Intermediate Speaking/Intermediate Reading/Intermediate Writing/Intermediate
Employee Benefits
Required by law:
勞保
健保
陪產假
產假
特別休假
育嬰留停
女性生理假
勞退提撥金
產檢假
就業保險
職災保險
其他值得一試的好工作
General Company | Mid-level
【半導體材料大廠】製程技術主管
生產管理主管/生產技術／製程工程師/特用化學工程師｜化學原料製造業｜高雄市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
試產／量產時的產品異常分析改善
生產成本控制
產品生產製程規劃及工時估算
負責生產製程管制與調配
合成研發
DSC
** 上市櫃公司，股價表現亮眼
** 與台灣一線半導體公司合作
** 與台灣一線半導體公司合作
1. 主導合成製程技術的開發、精進製程良率與生產穩定度。
2. 負責合成專業人才之技術培訓，建立具專業標準的作業體系。
3. 成本控制、原物料耗損管理及研發/生產資源配置。
4. 品質體系驅動與改善。
5. 熟 DCS系統，落實高度自動化生產監控與安全管理。
6. 擴廠與建廠戰略規劃
2. 負責合成專業人才之技術培訓，建立具專業標準的作業體系。
3. 成本控制、原物料耗損管理及研發/生產資源配置。
4. 品質體系驅動與改善。
5. 熟 DCS系統，落實高度自動化生產監控與安全管理。
6. 擴廠與建廠戰略規劃
Listed | Specialty Personnel
IC design工程師
半導體工程師｜半導體製造業｜新竹縣市全區｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
DRAM
Senior Analog circuit design engineer who meets one of following qualifications:
1. Proven track record on design of analog building blocks,
such as Bandgap reference, Charge pump, Regulator, Voltage reference.
2. Proven track record on design of high speed PHY and mixed-signal circuit,
such as High speed Transmitters and Receivers, DLL & DCC, PLL.
Familiar with DDR5 or LPDDR5 PHY design is a plus.
3. Proven track record on design of memory core circuit,
Such as Sense Amplifier, Word/Column Line driver and decoder, array architecture and floor planning.
Experience with DRAM design is a plus.
1. Proven track record on design of analog building blocks,
such as Bandgap reference, Charge pump, Regulator, Voltage reference.
2. Proven track record on design of high speed PHY and mixed-signal circuit,
such as High speed Transmitters and Receivers, DLL & DCC, PLL.
Familiar with DDR5 or LPDDR5 PHY design is a plus.
3. Proven track record on design of memory core circuit,
Such as Sense Amplifier, Word/Column Line driver and decoder, array architecture and floor planning.
Experience with DRAM design is a plus.
General Company | Junior
法務專案經理
法務｜半導體製造業｜新北市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
律師執照
高考律師
訴訟
國際法規遵循、中英文合約審閱、國內外爭訟管理、法律風險管理、法律議題研究與諮詢，其他交辦事項。
General Company | Junior
法務專案經理
法務｜半導體製造業｜新北市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
律師資格
高考律師
國際法規遵循、中英文合約審閱、國內外爭訟管理、法律風險管理、法律議題研究與諮詢，其他交辦事項。
Listed | Specialty Personnel
研發工程師主管
類比IC設計工程師/數位IC設計工程師｜IC設計相關業｜竹北｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
RTL
LDO
電源
有南部工作機會
PMIC
DC to DC
產品:車用/電池/PC/CHARGER
DC to DC
產品:車用/電池/PC/CHARGER
General Company | Specialty Personnel
Analog Engineer
類比IC設計工程師｜通訊機械器材相關業｜竹北｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
PLL
SerDes PHY
1. High speed SerDes PHY design;
2. MIPI C/D PHY Serdes analog circuit design.
2. MIPI C/D PHY Serdes analog circuit design.
General Company | Specialty Personnel
DV/ 數位ic 設計工程師
數位IC設計工程師｜通訊機械器材相關業｜竹北｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
EDA
Verilog
RTL
Verification of digital design ,most on serdes phy ip using UVM , including
.standard spec study/design feature study
.simple vip creation or third parity vip survey
.vplan define
.building sb/assertion check ,stimulus by constraint random
.create covergroup /assertion cover for functional coverage
.code coverage
.co –simulation with analog phy
.standard spec study/design feature study
.simple vip creation or third parity vip survey
.vplan define
.building sb/assertion check ,stimulus by constraint random
.create covergroup /assertion cover for functional coverage
.code coverage
.co –simulation with analog phy
General Company | Specialty Personnel
Sr. Digital/Logic Design Engineer
數位IC設計工程師/類比IC設計工程師｜IC設計相關業｜竹北｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
PCIE
USB
1. Design RTL/Logic using Verilog
2. Simulate and develop IPs and Subsystems
3. Validate silicon and debug
2. Simulate and develop IPs and Subsystems
3. Validate silicon and debug
