Sr. Digital/Logic Design Engineer

Senior Analog circuit design engineer who meets one of following qualifications:
1. Proven track record on design of analog building blocks,
such as Bandgap reference, Charge pump, Regulator, Voltage reference.
2. Proven track record on design of high speed PHY and mixed-signal circuit,
such as High speed Transmitters and Receivers, DLL & DCC, PLL.
Familiar with DDR5 or LPDDR5 PHY design is a plus.
3. Proven track record on design of memory core circuit,
Such as Sense Amplifier, Word/Column Line driver and decoder, array architecture and floor planning.
Experience with DRAM design is a plus.

PMIC
DC to DC
產品:車用/電池/PC/CHARGER

1. High speed SerDes PHY design;
2. MIPI C/D PHY Serdes analog circuit design.

Verification of digital design ,most on serdes phy ip using UVM , including   
.standard spec study/design feature study
.simple vip creation or third parity vip survey
.vplan define
.building sb/assertion check ,stimulus by constraint random
.create covergroup /assertion cover for  functional coverage
.code coverage
.co –simulation with analog phy

負責 Display Port IP 規劃與設計
工作內容:
 Display port IP leader
 Display port IP architecture definition
 RTL design and functional verification
 FPGA verification
 Synthesis and static timing analysis

1. 規劃集團 ESG策略
2. 制定集團大型專案計畫及相關執行方案
3. ESG團隊及業務管理

1.負責捷運專案的整體規劃、設計與實施管理。
2.確保項目在預算和時程內完成，並符合所有技術標準和規範。
3.協調內外部資源，管理項目的進度、風險與品質。
4.與政府機構、承包商、工程團隊保持有效溝通，解決專案中的各種問題與挑戰。
5.編制項目報告並向高層管理層匯報專案狀況，提出風險應對策略。
6.負責建立並管理項目團隊，確保各項工作順利進行。

領導樹脂開發團隊進行高分子配方設計、改質及功能驗證，建立電子級樹脂技術之核心競爭力。

主導 Underfill 與 TIM1 / TIM2 的產品開發路徑

專注於 CPO (Co-Packaged Optics) 相關封裝樹脂研究，針對下一代光學傳輸模組開發低介電、高可靠度且具備優異光學特性的封裝材料。

深度掌握材料於半導體封裝廠的製程實務，如點膠路徑、真空熟成、應力分析等，以確保產品與製程的高度相容性。

主導新產品開發流程，串接研發端與客戶需求，達成快速設計導入與規模化生產。