數位IC設計工程師/類比IC設計工程師/硬體研發工程師|IC設計相關業|台南市|Thỏa thuận trực tiếp
SystemVerilog
UVM
可在台南或新竹上班 薪資分紅,員工福利佳
Develop and maintain central DV flow and VIP. 2. Co-work with design team to define verification plan, strategies, and verify design at unit/block/chip level. 3. Technical consulting of various protocol VIPs