Analog Engineer

PMIC
DC to DC
產品:車用/電池/PC/CHARGER

負責 Display Port IP 規劃與設計
工作內容:
 Display port IP leader
 Display port IP architecture definition
 RTL design and functional verification
 FPGA verification
 Synthesis and static timing analysis

Senior Analog circuit design engineer who meets one of following qualifications:
1. Proven track record on design of analog building blocks,
such as Bandgap reference, Charge pump, Regulator, Voltage reference.
2. Proven track record on design of high speed PHY and mixed-signal circuit,
such as High speed Transmitters and Receivers, DLL & DCC, PLL.
Familiar with DDR5 or LPDDR5 PHY design is a plus.
3. Proven track record on design of memory core circuit,
Such as Sense Amplifier, Word/Column Line driver and decoder, array architecture and floor planning.
Experience with DRAM design is a plus.

Verification of digital design ,most on serdes phy ip using UVM , including   
.standard spec study/design feature study
.simple vip creation or third parity vip survey
.vplan define
.building sb/assertion check ,stimulus by constraint random
.create covergroup /assertion cover for  functional coverage
.code coverage
.co –simulation with analog phy

1. Design RTL/Logic using Verilog
2. Simulate and develop IPs and Subsystems
3. Validate silicon and debug

1. build up verilog testbench
2. fullchip verilog simulation/verification
3. verilog behavior models creation
4. pattern pool coverage raising up

1.負責捷運專案的整體規劃、設計與實施管理。
2.確保項目在預算和時程內完成，並符合所有技術標準和規範。
3.協調內外部資源，管理項目的進度、風險與品質。
4.與政府機構、承包商、工程團隊保持有效溝通，解決專案中的各種問題與挑戰。
5.編制項目報告並向高層管理層匯報專案狀況，提出風險應對策略。
6.負責建立並管理項目團隊，確保各項工作順利進行。

1.具建築開發、營建管理、不動產投資及市場策略擬定相關實務經驗。
2.擬定並執行集團整體營運計畫，推動中、長期發展策略，確保企業穩健成長與品牌價值提升。
3.制定、執行、追蹤各項經營績效指標，涵蓋土地開發、建案規劃、工程進度、銷售策略、財務預算與風險控管。
4.統籌工程、設計、業務、財務及行政後勤等單位運作，優化跨部門流程與管理效率。
5.審查各項投資開發案之可行性分析、成本控管與獲利評估，確保資源配置效益最大化。