IC Design Engineer / Semi-conductor Engineer
Semiconductor
新竹縣市全區
Face-to-face negotiation
Qualifications
數位晶片產品開發數位ic設計
Responsibilities
1.standard CMOS-based DRAM circuit design
2.full chip level simulation & verification
3.working with layout and CAD team
2.full chip level simulation & verification
3.working with layout and CAD team
Ideal Candidate
其他條件
以下符合幾項即可：
1.MS or above with major in EE related
2.familiar with EDA tools, such as virtuso
3.familiar with circuit simulation tools (HSPICE, finesim,etc.)
4.good knowledge of transistor level CMOS circuit design
5.experience in transistor level simulation
6.experience in memory circuit design is a plus
7.hand-on experience in verilog is a plus
以下符合幾項即可：
1.MS or above with major in EE related
2.familiar with EDA tools, such as virtuso
3.familiar with circuit simulation tools (HSPICE, finesim,etc.)
4.good knowledge of transistor level CMOS circuit design
5.experience in transistor level simulation
6.experience in memory circuit design is a plus
7.hand-on experience in verilog is a plus
Other Requirements
Education:Master
Department:Physics,Materials Science & Engineering,Electrical engineering
Experience:Over 3 years of experience
Management Responsibilities:Not need to bear any management responsibilities
Business trip:No business trip required
Department:Physics,Materials Science & Engineering,Electrical engineering
Experience:Over 3 years of experience
Language:
English：Listening/Intermediate Speaking/Intermediate Reading/Intermediate Writing/Intermediate
Business trip:No business trip required
Employee Benefits
Required by law:勞保 健保 陪產假 產假 特別休假 育嬰留停 女性生理假 勞退提撥金 產檢假 就業保險 職災保險
