關鍵能力
工作職責
2.full chip level simulation & verification
3.working with layout and CAD team
理想人選
以下符合幾項即可:
1.MS or above with major in EE related
2.familiar with EDA tools, such as virtuso
3.familiar with circuit simulation tools (HSPICE, finesim,etc.)
4.good knowledge of transistor level CMOS circuit design
5.experience in transistor level simulation
6.experience in memory circuit design is a plus
7.hand-on experience in verilog is a plus
其他條件
科系:物理相關科系,材料工程相關,電機相關科系
年資:3年以上工作經驗
出差外派:無需出差外派
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