1 10-12bit 1MSPS~5MSPS SAR ADC
2 10-12bit pipeline ADC
3 Switched-cap amplifier
4 Low-noise amplifier
5 Low-quiescent current bandgap and high-PSRR regulator

Experience in AXI / VCI / AHB master / slave bus and chip integration, Familiar with asic design flow.
Expertise in system issue debug, soc integration

1. 使用Verilog for RTL design
2. IPs 開發
3. 除錯與 silicon 驗證

SRAM Memory IP design

1. 負責standard cell architecture 開發