Qualifications
Responsibilities
2.full chip level simulation & verification
3.working with layout and CAD team
Ideal Candidate
以下符合幾項即可:
1.MS or above with major in EE related
2.familiar with EDA tools, such as virtuso
3.familiar with circuit simulation tools (HSPICE, finesim,etc.)
4.good knowledge of transistor level CMOS circuit design
5.experience in transistor level simulation
6.experience in memory circuit design is a plus
7.hand-on experience in verilog is a plus
Other Requirements
Department:Physics,Materials Science & Engineering,Electrical engineering
Experience:Over 3 years of experience
Business trip:No business trip required
Employee Benefits