IC Design Engineer
Semiconductor/Electronic
台北市
Face-to-face negotiation
Qualifications
SynthesisFPGARTLVerilog
Job Advantage
頂尖跨國電子設計製造商，並具完善的內部訓練與良好的職涯發展機會
Responsibilities
• Design and implementation of SoCs;
• RTL coding, verification, synthesis
• Work with FPGA engineers to perform early prototyping
• Support test program development, chip validation, and chip life until production maturity.
• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
• RTL coding, verification, synthesis
• Work with FPGA engineers to perform early prototyping
• Support test program development, chip validation, and chip life until production maturity.
• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
Ideal Candidate
• Knowledge of RTL logic design (Verilog), scripting languages (e.g., Perl, Python), revision control, and bug-tracking tools;
• Knowledge of scripting languages (e.g. Perl, Python), FPGA design, and/or embedded software tools (e.g. C, Assembly language, trace/debug); and
• Good writing and verbal communication skills.
• BA or MS (preferred) degree in EE/EECS/CS or equivalent.
• Knowledge of scripting languages (e.g. Perl, Python), FPGA design, and/or embedded software tools (e.g. C, Assembly language, trace/debug); and
• Good writing and verbal communication skills.
• BA or MS (preferred) degree in EE/EECS/CS or equivalent.
Other Requirements
Education:Undergraduate
Department:Electrical engineering
Experience:Over 5 years of experience
Management Responsibilities:Not need to bear any management responsibilities
Business trip:No business trip required
Department:Electrical engineering
Experience:Over 5 years of experience
Language:
English：Listening/Intermediate Speaking/Intermediate Reading/Intermediate Writing/Intermediate
Business trip:No business trip required
Employee Benefits
Required by law:勞保 健保 陪產假 產假 特別休假 育嬰留停 女性生理假 勞退提撥金 產檢假 就業保險 職災保險
