Sr. Digital/Logic Design Engineer

IC Design Engineer
Semiconductor/Electronic
台北市
Face-to-face negotiation
Foreign Company | Specialty Personnel 2022/07/11

Sr. Digital/Logic Design Engineer

IC Design Engineer
Semiconductor/Electronic
台北市
Face-to-face negotiation

Qualifications

ASIC design flowRTL

Responsibilities

1. 使用Verilog for RTL design
2. IPs 開發
3. 除錯與 silicon 驗證

Ideal Candidate

5+ years experiences with MS in EE

Other Requirements

Education:Master
Department:Engineering
Experience:Over 5 years of experience
Language:
English:Listening/Intermediate Speaking/Intermediate Reading/Intermediate Writing/Intermediate
Management Responsibilities:Not need to bear any management responsibilities
Business trip:No business trip required

Employee Benefits

Required by law:哺乳室,週休二日,勞保,健保,陪產假,產假,特別休假,勞退提撥金,產檢假,職災保險
Benefit system:員工紅利,員工配股,年終獎金,交通車,生育津貼,交通津貼補助,慶生會,停車位,優於勞基法特休,員工團體保險

Case Number:FC02003520

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