General Company | Specialty Personnel
資深 Cable工程師
產品事業處主管/產品設計師/專案經理｜ 其他電子零組件相關業 ｜中和區‧永和區 ｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
日期：2026/02/12 編號：F000013029
⭐️ Job Advantage
績優高頻Cable大廠
Qualifications
PFMEA
產品開發
Responsibilities
1. 接收國內/外客戶需求，制定產品規格提供。
2. 產品設計PFMEA、BOM表、PMP及產品圖面。
3. 線纜/線束產品開發與測試。
4. 材料選型及產品報價。
2. 產品設計PFMEA、BOM表、PMP及產品圖面。
3. 線纜/線束產品開發與測試。
4. 材料選型及產品報價。
Ideal Candidate
5. 協調銷售技術並提出產品相關問題的解決方案。
6. 英文精通。
7. 10年左右資歷
8. 薪資優可談
9. 上班地點：新北市中和區
6. 英文精通。
7. 10年左右資歷
8. 薪資優可談
9. 上班地點：新北市中和區
Other Requirements
Education:No Limitations
Department:Electronics engineering,Electrical engineering,Mechanical engineering
Experience:Over 10 years of experience
Language:
English：Listening/Fluent Speaking/Fluent Reading/Fluent Writing/Fluent
Management Responsibilities:Not need to bear any management responsibilities
Business trip:No business trip required
Language:
English：Listening/Fluent Speaking/Fluent Reading/Fluent Writing/Fluent
Employee Benefits
Required by law:
勞保
健保
陪產假
產假
特別休假
育嬰留停
女性生理假
勞退提撥金
產檢假
就業保險
職災保險
其他值得一試的好工作
General Company | Specialty Personnel
高頻高速連接器工程師
其他特殊工程師｜被動電子元件製造業｜汐止區｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
可靠度驗證
1. Server&Storage高頻高速連接器相關領域產品經驗尤佳
2. 新專案機構開發設計/結合高頻分析與測試結果進行設計改良與進度追蹤掌握
3. 專案跨部門溝通與整合
4. 圖面繪製/樣品測試/模具檢討
2. 新專案機構開發設計/結合高頻分析與測試結果進行設計改良與進度追蹤掌握
3. 專案跨部門溝通與整合
4. 圖面繪製/樣品測試/模具檢討
Listed | Specialty Personnel
FPGA 工程師
數位IC設計工程師｜自動控制相關業｜台北市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
VHDL
Verilog
RTL Coding
FPGA
上巿櫃IC設計褔利佳
1. FPGA implementation.
2. Integration of related FPGA (high-speed) interfaces.
3. System integration and verification.
4. FPGA Design, C/C++.
5. System simulation.
2. Integration of related FPGA (high-speed) interfaces.
3. System integration and verification.
4. FPGA Design, C/C++.
5. System simulation.
Listed | Specialty Personnel
研發工程師
數位IC設計工程師｜IC設計相關業｜新竹市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
RTL Coding
工作穩定 公司發展好
影像演算法、數位RTL Coding
General Company | Specialty Personnel
工程師
數位IC設計工程師｜IC設計相關業｜新竹縣市全區 ｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
數位電路驗證
數位晶片產品開發
RTL
1.EDA TOOL 客戶端支持服務
2.客戶bug解決
2.必要時支援on-site support
3.需熟悉Verilog及IC Flow
4.具獨立處理問題能力。
2.客戶bug解決
2.必要時支援on-site support
3.需熟悉Verilog及IC Flow
4.具獨立處理問題能力。
General Company | Specialty Personnel
研發工程師主管
其他工程研發主管｜光學器材製造業｜新竹市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
機構設計
軟韌體開發
1. AOI programming, system design and integration
2. Software writing (C, C++, Visual C++, MFC)
3. Requires knowledge related to imaging (image processing, image sensor, image quality, tuning, calibration, camera modules)
4. Software interface program modification.
5. Machine vision software design
2. Software writing (C, C++, Visual C++, MFC)
3. Requires knowledge related to imaging (image processing, image sensor, image quality, tuning, calibration, camera modules)
4. Software interface program modification.
5. Machine vision software design
General Company | Junior
研發主管
其他工程研發主管｜印刷電路板製造業(PCB)｜桃園市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
新技術開發
1. 新製程設立
2. 新產品導入
3. 重要VE與製程優化
4. Trouble shooting
5. 技術趨勢掌握與交流
6. 客訴處理
2. 新產品導入
3. 重要VE與製程優化
4. Trouble shooting
5. 技術趨勢掌握與交流
6. 客訴處理
General Company | Specialty Personnel
研發工程師/主管
數位IC設計工程師｜IC設計相關業｜苗栗縣市｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
RTL
1. TOP/Block physical implementation (28nm以下), 有12nm/7nm 經驗尤佳
2. IR rail analysis(Voltus/Redhawk)
3. Layout verification (Calibre DRC/LVS)
4. Timing closure (Tempus/PrimeTime/Tweaker)
5. Tcl/Perl/Makefile programming (有此技能者優先考量)
2. IR rail analysis(Voltus/Redhawk)
3. Layout verification (Calibre DRC/LVS)
4. Timing closure (Tempus/PrimeTime/Tweaker)
5. Tcl/Perl/Makefile programming (有此技能者優先考量)
Foreign Company | Specialty Personnel
Design Verification Engineer
數位IC設計工程師｜半導體製造業｜新竹縣市全區 ｜Salary negotiable (Regular monthly salary of NT$40,000 or above)
數位ic設計
Product : OLED DDI
1. Develop integrated verification environment.
2. Verify designs with system verilog and system verilog assertion.
3. Develop and optimize verification flow and methodology.
4. Good knowledge of IC design flow.
5. Scripting experience using scripting languages like Perl and Python.
1. Develop integrated verification environment.
2. Verify designs with system verilog and system verilog assertion.
3. Develop and optimize verification flow and methodology.
4. Good knowledge of IC design flow.
5. Scripting experience using scripting languages like Perl and Python.
