資深數位IC設計工程師/主管

Engineering/R&D
Semiconductor/Electronic
新竹縣市全區
Face-to-face negotiation
General Company | Specialty Personnel 2024/03/05

資深數位IC設計工程師/主管

Engineering/R&D
Semiconductor/Electronic
新竹縣市全區
Face-to-face negotiation

Qualifications

FPGAVerilogRTL

Responsibilities

1. Verilog Coding of the digital part of the power IC, FPGA, familiar with 8051/ARM CPU is preferred.
2. Experience in power supply IC design and fan motor motor control system is preferred.

Ideal Candidate

數位設計
FPGA
馬達控制演算法

Other Requirements

Education:No Limitations
Department:No Limitations
Experience:Over 5 years of experience
Language:
No Limitations
Management Responsibilities:Not need to bear any management responsibilities
Business trip:No business trip required

Employee Benefits

Required by law:勞保 健保 陪產假 產假 特別休假 育嬰留停 女性生理假 勞退提撥金 產檢假 就業保險 職災保險

Case Number:F000009887

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